During the early 1990s, the Peripheral Component Interconnect (PCI) standard was introduced. PCI provided direct access to system memory for connected devices, but uses a bridge to connect to the frontside bus and to the CPU. PCI can connect multiple components. A PCI bridge chip regulates the speed of the PCI bus independently of the CPU's speed to enable a higher degree of reliability and to ensure that PCI-hardware manufacturers have consistent design constraints. PCI supports Plug and Play which enables a device or card to be inserted into a computer and automatically recognized and configured to work with the system.
Today's software applications are more demanding of the platform hardware, particularly the I/O subsystems. Streaming data from various video and audio sources are now commonplace on the desktop and mobile machines. Applications such as video-on-demand and audio redistribution are putting real-time constraints on servers too. The PCI architecture no longer is able to cope with these demands and a new standard has been proposed called PCI Express.
Referring to FIG. 1, there is illustrated a PCI Express topology 100 that would be included in a computing device. The topology contains a Host Bridge 101 and several endpoints 104–109 (i.e., the I/O devices) in addition to a CPU 102 and memory 103. Multiple point-to-point connections are accomplished by a switch 110. The switch 110 replaces the multi-drop bus used by PCI and is used to provide fan-out for the I/O bus. The switch 110 may provide peer-to-peer communication between different endpoints 104–109, and this traffic if it does not involve cache-coherent memory transfers, need not be forwarded to the host bridge 101. The switch 110 is shown as a separate logical element but it could be integrated into the host bridge 101.
While this is an improvement over the older PCI architecture, it does not provide a way to connect and share end points among different computing devices. Thus, there is a need for a system and method of sharing of end points. Such a system would greatly enhance the flexibility of computing devices, as well as provide for methods to reduce power consumption. The present invention provides such a solution.